Binu R. Chandran has 20 years of experience, with 16 years in VLSI design verification and 4 years in program management and accounts management. He has experience in handling teams of over 75 members at client locations in Malaysia and Offshore Development Centers (ODC) in Bangalore, Kochi, Vizag, Ahmedabad, and Penang. Binu has successfully discussed new projects with clients, submitted proposals, obtained approvals, and coordinated with teams for improvements based on client feedback. He possesses extensive expertise in SoC full chip design verification, subsystem/IP verification, FPGA design and verification, and has significant technical and project management experience. Binu is well-versed in PCIe IP verification from Gen 1 to Gen 4, and has exposure to various industrial domains including automotive, computing, consumer electronics, networking, and aerospace. Binu has substantial verification experience using tools from Synopsys (VCS, Verdi), Mentor Graphics (ModelSim, Questa), and Cadence (NCVHDL, NCVerilog, Xcelium). He is proficient in VHDL, Verilog HDL, and System Verilog (UVM, OVM), and has designed systems based on Altera, Actel, Lattice, and Xilinx FPGAs. Binu has worked on protocols such as UART, ARINC 429, and L2-L4 (Ethernet, TCP, IP, etc.) protocols. He has utilized EDA tools like Synopsys VCS, Altera Quartus II, Actel Libero, Lattice Diamond, Synplify Pro, ModelSim, Xilinx ISE, and Cadence NC-VHDL/NC-Verilog/Simvision. Additionally, he has employed project support tools including Perforce, Accurev, Serera VM, DOORs, and PVCS Tracker. Binu is experienced in the bring-up, debugging, and testing of Actel and Xilinx FPGAs. He is recognized for his strong communication and leadership skills and is an IEEE Senior Member (#90892441).